“instruction set”可以造什么句，instruction set造句

I want to see which instruction set is used.

To learn more about Parrot's instruction set, check out the opcodes available within it.

UNIX-based environments are often 64-bit, and most UNIX vendors don't support the x86 instruction set.

This article discusses how to edit ladder scheme under instruction set called fully in accordance with the technological process.

Through analyzing the methods of branch prediction proposed in recent years, I bring forward a hybrid branch prediction scheme which ADAPTS well to MIPS instruction set.

Underlying the front-end parsers is a symbolic instruction set – a kind of portable assembly code – which can be translated to any of the supported machine architectures.

Simulation in real time. One computer emulates another by executing an emulato r in such a way as to behave like the latter ( for instance, it interprets the sa me instruction set ).

The term bytecode evolved from implementations that efficiently implemented their virtual instruction sets as single bytes for simplicity and performance.

It defines a virtual instruction set.

As with any instruction set, the Ant syntax is unable to express certain concepts.

Its successor was the 4040 processor (released in 1974), which had an expanded instruction set, program memory, register set, and stack.

I bet a lot of people continued to write machine language until the processor, like a bartender eager to close up and go home, finally kicked them out by switching to a RISC instruction set.

Conscious: Why would you take the time to create all of these instruction sets if you never want to share them with me?

It only CARES that the ones and zeros are consistent with its instruction set and address space.

Both had custom instruction sets, with programs designed in their raw machine code.

Program instruction set, logic stack and data type of I/O memory which are tied up with tasks in the soft-PLC system are analyzed and studied.

It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.